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Due to the recent progress in deep learning and neural acceleration architectures, specialized deep neural network or convolutional neural network (CNNs) accelerators are expected to provide an energy-efficient solution for real-time vision/speech processing, recognition and a wide spectrum of approximate computing applications. In addition to their wide applicability scope, we also found that the...
Reusing network-on-chip (NoC) as test-access-mechanism (TAM) has been adopted to transfer test data to embedded cores. However, an observation shows that compared to NoC-reuse TAM, some bus-based TAM are able to achieve better results in test time due to its fine-grained scheduling unit. This paper proposed a new TAM named Test Tree(T2). T2TAM could be built by reusing the hardware resources of routers...
An embedded test stimulus decompressor is presented for the test patterns decompression, which can reduce the required channels and vector memory of automatic test equipment (ATE) for complex processor circuit. The proposed decompressor mainly consists of a periodically alterable MUX network which has multiple configurations to decode the input information flexibly and efficiently. In order to reduce...
Memory faults are major forms of software bugs that severely threaten system availability and security in C/C++ program. Many tools and techniques are available to check memory faults, but few provide systematic full-scale research and quantitative analysis. Furthermore, most of them produce high noise ratio of warning messages that require many human hours to review and eliminate false-positive alarms...
An embedded test stimulus decompressor is presented to generate the test patterns, which can reduce the required vector memory and channels of automatic test equipment (ATE). The decompressor consists of a periodically alterable MUX network which has multiple configurations to decode the input information flexibly. A complete synthesis flow is presented to generate the MUXs network automatically....
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