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In this paper, we present active and passive performances of the 65 nm LP SOI HR technology from STMicroelectronics and two simulated circuits to illustrate the potentiality of the technology for millimeter wave (mm-wave) applications. 65 nm low power (LP) partially depleted (PD) n-MOSFET floating body (FB) shows a f/fmax of 160/200 GHz. Coplanar waveguides (CPW) present a measured attenuation constant...
A 1 stage and 3 stages 80 GHz low noise amplifiers (LNA) are presented in this paper. Both mm-wave LNA are integrated in a 65 nm CMOS SOI process. The one stage amplifier exhibits 2.1 dB gain and a noise figure of 4.5 dB at 80 GHz. The input and output return losses are -13 dB and -6 dB respectively. This amplifier consumes 22 mW from a supply voltage of 1.2 V and occupies an area of 0.64 mm2 including...
This paper presents a low area, low consumption, 40 GHz low noise amplifier (LNA), a down-converter and an oscillator, from which the performance of a 40 GHz wireless receiver can be estimated. The circuits were realized using a post-processing BCB above-IC technology and 0.13 mum SiGe:C BiCMOS HBT process, and their performance are compared with those obtained on circuits without post-processing...
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