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This paper presents a modular verification approach for asynchronous circuits to address state explosion with a novel interface refinement method to reduce false counterexamples.This method borrows the idea of parallel composition, and it iteratively refines each component in a design by examining its interface interactions, and removes the behavior not synchronized with its neighbors. This method...
We present a graph model and an ILP model for optimal TAM design for transparency-based SoC testing. The proposed method is an extension of (Chakrabarty, 2003) so that not only the system-level cost but also the core-level cost can be simultaneously taken into consideration during the optimization process. We also relax the constraints by considering test dataflows and extend it to be able to handle...
This paper presents a decomposition-based method for timed circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesizes each output individually. It begins by contracting the timed signal transition graph (STG) to include only transitions on the output of interest and its possible trigger signals. Next, the reachable state space for this contracted...
An integrated test scheduling methodology for multiprocessor system-on-chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set...
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