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This paper presents a high performance and power efficient architecture for motion estimation (ME). For this architecture two algorithms are implemented, a Sub-sampled Diamond Search (SDS) and a Quarter Sub-sampled Diamond Search (QSDS), both with Dynamic Iteration Control (DIC) algorithm. The SDS-DIC and QSDS-DIC algorithms can significantly reduce the number of SAD (Sum of Absolute Difference) calculations...
This paper presents the standard-cells synthesis and comparison of parallel hardware architectures for the Sum of Absolute Differences (SAD) datapath, focusing on different design points such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (isoperformance target). Clock gating and different combination of parallelism and pipeline architectural...
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