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This paper presents a new method for high efficiency video coding using an adaptive GOP structure based on video content for the H.264/AVC standard. The available H.264/AVC encoders typically use static GOP sizes that define how the frames I (Intra), P (Predictive) and B (Bi-predictive) are positioned during de coding process. However, by analyzing the video content it is possible to identify the...
The spatial scalability is one of the main features in scalable video coding and it provides an efficient video representation with different spatial resolutions. This paper presents a high throughput scalable motion compensation architecture compliant with the H.264/SVC standard. The designed architecture is able to decode two dyadic spatial layers, it includes the Motion Compensation in these two...
This work presents an intra frame prediction hardware architecture for H.264/AVC baseline/main profile encoder which performs real time processing of HDTV 1080p videos. It is achieved by exploring the parallelism of intra prediction and by reducing the latency for Intra 4times4 processing, which is the intra encoding bottleneck. Synthesis results on Xilinx Virtex-II Pro FPGA and TSMC 0.18 mum standard-cells...
Amongst the video compression standards, the latest one is the H.264/AVC. This standard reaches the highest compression rates when compared to the previous standards. On the other hand, it has a high computational complexity. This high computational complexity makes it difficult the development of software applications running in a current processor when high definitions videos are considered. Thus,...
This paper presents a low cost and memoryless hardware design for the context adaptive variable length decoder (CAVLD) of the H.264/AVC video coding standard. Usually, a large number of memory bits and memory accesses are required to decode the CAVLD symbols in H.264/AVC since a great number of syntax elements are decoded based on look-up tables. This is an important problem given the high hardware...
This work presents a new method for hardware functional verification through parallel co-simulation within complex systems using PLI as a mechanism of interface between hardware (HW) and software (SW). This method consists in the HW/SW parallel simulation using a transparent communication between these modules provided by a handshake mechanism that ensure the synchronism between the parts. The discussion...
This paper presents a high throughput hardware architecture for forward transforms module of H.264/AVC video coding standard. The designed architecture can reach 303 MHz, when mapped to a Xilinx Virtex II Pro FPGA, and it is able to process 4.9 billion of samples per second. This throughput allows the use of the designed architecture in H.264/AVC codecs targeting real time when processing high resolution...
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