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Silicon(Si)/graphene composite has been regarded as one of the most promising candidates for next generation anode materials with high power and energy density in lithium ion batteries. Introduction of graphene in Si anodes could improve the electronic conductivity, suppress the severe volume expansion of Si, and facilitate the formation of stable solid electrolyte interphase, etc. However, traditionally...
Nowadays, 2.5D and 3D stacked die technologies are under prosperous development for the benefit of transistor scaling and performance. However, with the trend of higher electrical performance, lower power consumption and cost effective demand, Non-TSV interposer (NTI) is one of the ways to meet the requirement. This paper introduces and demonstrates the NTI process flow, which includes chip-on-wafer...
A 330,000 gate field programmable gate array (FPGA) VS12C fabricated on 0.2μm full-depletion silicon-on-insulator (FD SOI) process is presented and the test results indicate this chip has the lower power and higher tolerance to radiation compared with Xilinx radiation-hardened XQVR300 chip implemented on 0.22μm epitaxial silicon. This paper demonstrates the benefit of the FD SOI technology on low...
The paper describes the parasitic structures of MOS transistors in SOI CMOS ICs at first. Then the influences of the parasitic structures on single particles radiation effect of MOS transistors in SOI CMOS ICs are presented. Finally the hardness methods of single event effects resulted by the parasitic structures of MOS transistors are given and the estimate about their excellence is made out.
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