The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The software and digital is the development trend of vector network analysis. Combined with the idea of software radio, this paper presented a design scheme of vector network analyzer and discussed the key technologies and implementation. Firstly this paper studied the principle and composition of vector network analyzer, the overall design of the system hardware was given. Secondly, we discussed...
In order to solve the problems in High-speed network that the general software methods of traffic classification cannot meet the requirements of real-time; a method of Naïve Bayes based on FPGA for network traffic classification was proposed. This method is using Naïve Bayes based on FPGA for the network traffic classification, whose classification decisions can be reconfigured on the basis of classification...
Multi-dimensional packet classification is often the performance bottleneck for network devices. For low-cost high performance embedded networking applications, the best solution could be doing packet classification by specially designed hardware which can effectively release the burden of system CPU. We have realized a compact FPGA-based packet classification coprocessor in an embedded system using...
The encoding and decoding rules of 64B/66B and inherent characteristic among 64B/66B codes are studied in this paper. A hardware implementation of 64B/66B encoder/decoder is introduced, which combines the advantages of lookup-table and logic analysis methods with low resource consumption, High speed and high reliability. The algorithm of encoding and decoding is described with Verilog HDL, and was...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.