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Asynchronous self-timed circuits which tolerate any delay variations are a feasible solution to timing-related problems while they suffer large energy dissipation due to large amount of their circuits. In future process technologies, it has been recognized that leakage power is a large factor in the total power dissipation. In this paper, we propose two leakage power reduction methods for m-out-of-n...
In this paper, we propose a design method for low-power self-timed combinational circuits and latches based on the 1-out-of-4 encoding method. We propose a 1-out-of-4 latch circuit using standard cell libraries in order to establish a semi-custom low-power self-timed design style. The energy consumption of the proposed circuits is about 18% average smaller than that of conventional dual-rail encoded...
As the VLSI technology advances, delay variations become extremely large. Delay variation properties caused by various variation factors are different. However, the characteristics of delay variations have not been considered in traditional delay models or asynchronous design styles, which have, therefore, suffered large performance overhead. In this paper, we propose the following two methods for...
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