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This paper reports a 0.5V SOI CMOS dynamic-threshold MOS (DTMOS)/ dual-threshold (MTCMOS) circuit technique for design optimization of low-power SOC applications. Via the DTMOS/non-DTMOS technique for implementing the SOI version of the gate-level dual-threshold static power optimization methodology (GDSPOM), a 16-bit multiplier circuit has been designed, showing a performance with 30% less power...
A performance evaluation and circuit architecture for all-digital data recovery using an oversampling method is proposed. The architecture is very regular and hence very suitable for standard-cell implementation flow. Due to its feedforward architecture, the required bit-rate can be achieved through proper pipelining. These properties make the proposed architecture very suitable as soft silicon intellectual...
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