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In this paper, we propose a simple trench-oxide thin-film transistor (TO TFT) process for 1T-DRAM applications. Our proposed TO TFT structure has several novel features as follows: 1. The buried oxide and the isolation oxide are carried out simultaneously in order to achieve a goal of simple process. 2. The trench design is used to improve both the sensing current windows (~ 84%) and the retention...
This paper for the first time presents a performance comparison between junction and junctionless thin-film transistors (TFTs) by using TCAD simulations. Note that the DIBL and S.S. of a junctionless TFT (JLTFT) are larger and higher, respectively, than those of its junction TFT (JTFT) counterpart. Although the JLTFT gets a higher current drive based on the same Vov as compared with the JTFT, its...
In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 ION/IOFF current ratio.
In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.
In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.
In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and...
This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature;...
In this paper, we propose a novel self-aligned silicon-on-insulator (SOI) MOSFET with Omega-shaped conductive layer and source/drain-tie (SA-OmegaCFET). Based on the TCAD 2D simulation results, we find that combining the applications of a nature Source/Drain (S/D) tie with a recessed S/D region can effectively improve the issue of self-heating effects, but without losing control of the short-channel...
This paper investigates the device behaviours of a pseudo tri-gate ultra-thin-channel vertical MOSFET with source/drain tie. For comparison two transistors are designed. According to the 2D simulation, our proposed structure can effectively enhance the drain current and the thermal stability, mainly due to the ultrathin channel (Tsi = 10 nm). The fabricated device have very low subthreshold swing...
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