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In this work, we present a cost effective Cu electroless (ELD-Cu) metallization scheme in which through-silicon vias (TSVs), can be scaled towards higher aspect ratios. We successfully integrated 30 nm ELD-Cu on 15 nm Ru in 3×50 µm TSVs on 300 mm wafer scale and found excellent electrical reliability. Cost calculations revealed the major impact of the implementation of the platable Ru liner material...
We demonstrate electrically functional 0.099 μm2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with Lg˜40 nm, 12-17 nm wide Fins, and cell β ratio...
The effect of ash chemistry on dielectric constant of blanket and patterned low-k was studied using a near-field scanning probe microwave microscope, known commercially as NeoMetriKTM technology. Two common photoresist ash approaches with the same etch sequence were studied: plasma assisted sublimation of photoresist at elevated temperature and ion-assisted ash at room temperature. The results for...
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