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A fully differential common-source cascode low noise amplifier(LNA) is presented for wireless receivers. The capacitive cross-coupling technique combined with cascode transistor is introduced to enhance LNA gain and reduce noise figure as well as the nonlinearity influence of cascaded transistors. A 2.6 mm long on-chip folded dipole antenna is integrated with this LNA and co-design is performed for...
This paper presents a 64-bit subword-parallel multiplier capable of supporting multiple precisions. The proposed multiplier uses novel correction-value merging technique to perform one 64times64, two 32times32 or four 16times16 bit unsigned/signed multiplication operations in parallel. The multiplier is implemented in 0.18 mum CMOS process. Critical path delay is 2.88 ns and layout area is 1.65 mm...
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