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Outlier screening is a popular approach for testing automotive products. In practice, developing an outlier model can be subjective, making justification of the model challenging. In this paper we propose a new concept called Consistency which provides a data-driven objective way to assess an outlier model. We study the development of outlier models in view of this new model consistency concept and...
Univariate outlier analysis has become a popular approach for improving quality. When a customer return occurs, multivariate outlier analysis extends the univariate analysis to develop a test model for preventing similar returns from happening. In this context, this work investigates the following question: How simple multivariate outlier modeling can be? The interest for answering this question are...
Burn-in is a common test approach to screen out unreliable parts. The cost of burn-in can be significant due to long burn-in periods and expensive equipment. This work studies the potential of using parametric test data to reduce the time of burn-in. The experiment focuses on developing parametric test models based on test data collected after 10 hours of burn-in to predict parts likely-to-fail after...
In a market where quality requirements are extremely high; the ultimate goal is to improve test quality and reduce the occurrence of test escapes. A customer return is a test escape which passes all tests but fails in the field. This paper analyzes seven lots of parametric wafer probe test data, where each lot contains one customer return. We ask a fundamental question: What subset of tests provides...
This paper presents a novel behavioral-level analog circuit performance modeling methodology using kernel based support vector machine (SVM). Behavioral modeling for analog circuits is in high demand for architectural exploration and system prototyping of increasingly complex electronic systems. In this paper, we investigate the effectiveness of applying SVM to model analog circuits. Based on the...
For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how features...
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