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Modern IC design and manufacturing have progressed in leaps and bounds, resulting in unimaginable integration, and power-performance advancements. This progress has been accompanied by adverse design-layout-process interactions and increased defect sensitivity. Controlling these complex interactions has exacted a steep price in terms of delaying yield ramp, extending silicon validation to characterize...
One of the challenges of functional test content optimization, in the context of performance validation, is to predict from a high level model an event of interest observed in either a detailed simulation or in silicon testing. This work uses peak power validation as an example to study the potential of using learning algorithms to uncover the correlations between the different levels of abstraction...
Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related...
The detection of speed-related defects relies on fault excitation and propagation along critical speed paths in the design. Different types of structural tests detect speed paths differently. In this paper, we compare the capabilities of speed path detection using Ndetect and timing-aware transition tests on silicon. Experimental data on the latest quad-core AMD Opteron?? processor is collected. Results...
Due to the magnitude and complexity of design and manufacturing processes, it is unrealistic to expect that models and simulations can predict all aspects of silicon behavior accurately. When unexpected behavior is observed in the post-silicon stage, one desires to identify the causes and consequently identify the fixes. This paper studies one formulation of the design-silicon mismatch problem. To...
Traditional diagnosis of defects is based on an assumed fault model. A failing chip is diagnosed to find the subset of faults that can best explain the failure. This paper illustrates a link between this traditional perspective of diagnosis and a new perspective where diagnosis is seen as a form of data learning. We explain that both defect diagnosis and data learning are solving so-called ill-posed...
For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how features...
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