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A new additive ultra-thin chip fabrication process is presented, utilizing an array of vertical anchors that mechanically connect silicon membrane chips to a standard silicon wafer. The process is demonstrated down to 8 μm silicon chip thickness, with a chip thickness control better than ±0.2 μm and a surface topography with average roughness <; 7 nm. Such pre-processed wafers can be used for CMOS...
Plastic electronics, thin-film-transistors on foil and ultra-thin chips on foil are technologies currently pursued to support the strongly emerging market for flexible electronics. Ultra-thin CMOS chips on foil will not only provide solutions whenever high circuit performance and/or complexity are required but also in a heterogeneous integration with organic or TFT electronic components on foil, such...
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