Search results for: J.P. Colinge

Items from 1 to 20 out of 33 results

article

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

J.P. Colinge, A. Kranti, R. Yan, C.W. Lee, more

Solid State Electronics > 2011 > 65-66 > Complete > 33-37

Junctionless transistors are variable resistors controlled by a gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The electrical characteristics are identical to those of normal MOS-FETs, but the physics is quite different. Conduction mechanisms in Junctionless Nanowire Transistors (gated resistors) are compared to inversion-mode and...

chapter

Analysis of the Low-Frequency Noise of Junctionless Nanowire Transistors operating in saturation

R.T. Doria, R.D. Trevisoli, M. de Souza, J.P. Colinge, more

IEEE 2011 International SOI Conference > 1 - 2

2011 IEEE International SOI Conference

This work presented the LF noise behavior of nMOS JNTs investigated by experimental results. It was shown that JNTs can present either 1/ƒ or 1/ƒ² noises, depending on their operation region and the frequency. 1/ƒ noise has been associated to carrier number fluctuations whereas 1/ƒ² can be related to defects in the depletion layer. The W_mask reduction degrades S_Id at higher V_GT (∼ 1 V) and present...

article

Variable temperature characterization of low-dimensional effects in tri-gate SOI MOSFETs

C. Barrett, D. Lederer, G. Redmond, W. Xiong, more

Solid State Electronics > 2010 > 54 > 11 > 1273-1277

We report on variable temperature charge transport measurements of tri-gate silicon-on-insulator MOSFETs with fin widths of 11nm, fin heights of 58nm and gate lengths ranging from 80nm to 250nm. Reproducible inflection points were observed in drain current vs. gate voltage data acquired at low temperature (4–8K) and low drain bias (0.1mV), yielding oscillations in the extracted transconductance data...

chapter

LDD depletion effects in thin-BOX FDSOI devices with a ground plane

R. Yan, R. Duane, P. Razavi, A. Afzalian, more

2009 IEEE International SOI Conference > 1 - 2

2009 IEEE International SOI Conference

In this paper, we analyze LDD depletion effects in fully-depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). LDD engineering is introduced to reduce the source and drain resistance and threshold voltage shifts. Short-channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15 nm.

chapter

SOI gated resistor: CMOS without junctions

J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti, more

2009 IEEE International SOI Conference > 1 - 2

2009 IEEE International SOI Conference

We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.

chapter

Variable-barrier tunneling SOI transistor (VBT)

A. Afzalian, N. Dehdashti, I. Ferain, C.W. Lee, more

2009 IEEE International SOI Conference > 1 - 2

2009 IEEE International SOI Conference

In this paper, we report the possibility of achieving sub-kT/q subthreshold slope (i.e. lower than 59.6 mV/decade at T=300 K) without using either impact ionization or band-to-band tunneling. The device uses intraband tunneling within the conduction band through barriers whose shape varies with the applied gate voltage. Subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported...

chapter

Hot carrier (HC) and bias-temperature-instability (BTI) degradation of MuGFETs on silicon oxide and silicon nitride buried layers

C.-W. Lee, I. Ferain, A. Afzalian, K.-Y. Byun, more

2009 Proceedings of the European Solid State Device Research Conference > 261 - 264

39th European Solid-State Device Research Conference. ESSDERC 2009

The results are reported of an experimental study of the hot carrier (HC) and bias-temperature-instability (BTI) reliability of MuGFETS, fabricated on SOI wafers with silicon oxide and silicon nitride buried layers. N- and P-channel devices of 65 nm long and 42 nm or 32 nm wide channels were stressed and measured at room temperature and at 125degC. A complicated picture emerges: HC degradation is...

article

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

Ran Yan, Danny Lynch, Thibault Cayron, Dimitri Lederer, more

Solid State Electronics > 2008 > 52 > 12 > 1872-1876

In this paper, we investigate random doping fluctuation effects in trigate SOI MOSFETs by solving the three-dimensional (3D) Poisson, drift-diffusion and continuity equations numerically. A single doping impurity atom is introduced in the undoped channel region of the device and the resulting shift of threshold voltage is measured from the simulated I–V characteristics. This enables the derivation...

chapter

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET

W. Xiong, C.H. Hsu, C.R. Cleavelin, M. Ma, more

2007 IEEE International SOI Conference > 35 - 36

2007 IEEE International SOI Conference

The origin of the large Vt shift observed in planar FDSOI is the creation of negative charge states in the BOX by F implant. F implant is a suitable approach for planar FDSOI SoC integration with single WF metal gate, but NOT for MuGFETs. F implant degrades electron mobility and the degradation is a function of F dose. The hole mobility is unaffected by F implant.

chapter

Multi-Gate SOI MOSFET Operations in Harsh Environments

W. Xiong, C.R. Cleavelin, C.H. Hsu, M. Ma, more

2007 IEEE International SOI Conference > 29 - 30

2007 IEEE International SOI Conference

This paper reviews MuGFET (multi-gate MOSFET) devices performance under extreme temperature range (5-573 K) and total radiation dose up to 6 Mrad. It is concluded that MuGFET is not only a good platform for CMOS scaling, but also an excellent platform for operation in harsh environments.

chapter

A Quantum Definition of Threshold Voltage in MuGFETs

Se Re Na Yun, Chong Gun Yu, Jong Tae Park, Chi-Woo Lee, more

2007 IEEE International SOI Conference > 137 - 138

2007 IEEE International SOI Conference

The dependence of threshold voltage on device dimensions and number of gates is analyzed. A new definition of threshold voltage, based on quantum-mechanical considerations, is proposed.

article

Multi-gate SOI MOSFETs

J.P. Colinge

Microelectronic Engineering > 2007 > 84 > 9-10 > 2071-2076

This paper describes the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, Π-gate, Ω-gate and gate-all-around) structures. Increasing the “effective number of gates” improves the electrostatic control of the channel by the gate and, hence, reduces short-channel effects. Due to the very small dimensions of the devices, one-and two-dimensional confinement effects...

article

Dose radiation effects in FinFETs

Xusheng Wu, Philip C.H. Chan, A. Orozco, A. Vazquez, more

Solid State Electronics > 2006 > 50 > 2 > 287-290

This paper reports the effects of dose irradiation on FinFETs. A threshold voltage shift of 100mV is observed after irradiation at a dose of 300krad(SiO ₂ ). The creation of oxide charges reduces the threshold voltage at the bottom of the device, while the generation of interface traps increases the threshold voltage at the sidewalls of the fin. The leakage current and the subthreshold slope...

article

Influence of device geometry on SOI single-hole transistor characteristics

X. Tang, X. Baie, J.P. Colinge, P. Loumaye, more

Microelectronics Reliability > 2001 > 41 > 11 > 1841-1846

SOI single-hole transistors have been fabricated by intentionally converting a quantum wire to an island connected to source and drain by two narrow constrictions. Two devices with different constriction lengths were investigated. It is found that slight differences in constriction lengths can lead to dramatic differences in device characteristics. For the device with short constrictions, periodic...

article

Hall effect measurements in double-gate SOI MOSFETs

A. Vandooren, S. Cristoloveanu, D. Flandre, J.P. Colinge

Solid State Electronics > 2001 > 45 > 10 > 1793-1798

The electron mobility and concentration in double-gate silicon-on-insulator (SOI) gate-all-around transistors is extracted by Hall effect measurements at room and liquid nitrogen temperature. The Hall mobility is compared with the drift mobility determined from the transconductance measurement of the devices in strong inversion. The results of this study indicate that the method based on I _D ...

article

High-temperature instability processes in SOI structures and MOSFETs

A.N. Nazarov, V.I. Kilchytska, Ja.N. Vovk, J.P. Colinge

Journal of Telecommunications and Information Technology > 2001 > nr 1 > 18-26

The paper reviews the problems related to BOX high-temperature instability in SOI structures and MOSFETs. The methods of bias-temperature research applied to SOI structures and SOI MOSFETs are analysed and the results of combined electrical studies of ZMR, and SIMOX SOI structures are presented. The studies are focused mainly on electrical discharging processes in the BOX at high temperature and its...

article

Self-aligned silicon-on-insulator nano flash memory device

X. Tang, X. Baie, J.P. Colinge, A. Crahay, more

Solid State Electronics > 2000 > 44 > 12 > 2259-2264

This paper reports on the fabrication of a silicon-on-insulator nano flash memory device based on the differential oxidation rate of silicon resulting from gradients in the arsenic doping concentration. The key processes involved are the formation of the desired arsenic doping profile, electron beam lithography and wet oxidation. The resulting device is a triangular-channel MOSFET with a nanocrystal...

chapter

Recombination Current and Carrier Lifetime Extraction in Dual-Gate Fully Depleted SOI Devices

T. Ernst, S. Cristoloveanu, A. Vandooren, J.P. Colinge, more

28th European Solid-State Device Research Conference > 272 - 275

28th European Solid-State Device Research Conference

article

Silicon-On-Insulator-Based Technology MOSFET : Prospects For Application to Low Noise RF Integrated Circuits

G. Dambrine, J.P. Raskin, F. Danneville, D. Vanhoenacker, more

00028th European Microwave Conference, 01998 > 1998 > 1 > 721 - 726

28th European Microwave Conference, 1998

An exhaustive study of the high frequency four noise parameters of SOI-MOSFET, as function of various gate geometries (length, width, gate resistivity), is proposed. The emphasis is on high frequency noise modeling and measurement of SOI-MOSFET. We show that it is crucial to take into account both gate and drain noise sources in the case of these high performance devices. The high level of MOSFET...

article

Comparison of self-heating effect in GAA and SOI mosfets

P. Francis, J.P. Colinge, D. Flandre

Microelectronics Reliability > 1997 > 37 > 1 > 61-75

An analytical model is developed to estimate the effect of the scaling of the buried oxide on the heat flow in SOI devices. The heat evacuation is shown to follow the buried oxide thickness to the n-th power with -0.5 > n > -1, and it strongly depends on device dimensions. Three experimental independent evidences of reduced self-heating in GAA devices are provided and analyzed in the light...

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SILICON (8)
ELEMENTAL SEMICONDUCTORS (6)
MOSFET (6)
SILICON-ON-INSULATOR (6)
THRESHOLD VOLTAGE (6)
LOGIC GATES (5)
MUGFET (4)
SOI (4)
CMOS CIRCUITS (3)
INSULATED GATE FETS (3)
MOSFETS (3)
RING OSCILLATORS (3)
SEMICONDUCTOR GROWTH (3)
CARRIER LIFETIME (2)
CHARGE CARRIER LIFETIME (2)
CMOS INTEGRATED CIRCUITS (2)
CURRENT MEASUREMENT (2)
DATA MINING (2)
DOPING (2)
FILMS (2)
INSULATED GATE FIELD EFFECT TRANSISTORS (2)
MOBILITY (2)
MOS TRANSISTORS (2)
N-CHANNEL DEVICES (2)
OSCILLATORS (2)
SELECTIVE ANNEALING (2)
SEMICONDUCTOR DEVICE MODELING (2)
SEMICONDUCTOR DEVICE MODELS (2)
SEMICONDUCTOR-INSULATOR BOUNDARIES (2)
SI (2)
SI-SIO₂ (2)
SILICON ON INSULATOR TECHNOLOGY (2)
SILICON-ON-INSULATOR TECHNOLOGY (2)
SOI MOSFET (2)
THICKNESS MEASUREMENT (2)
THIN FILM TRANSISTORS (2)
THIN SIMOX FILMS (2)
TRANSISTORS (2)
(100) RECRYSTALLISED FILM (1)
0.7 V (1)
2.9 FJ (1)
3D SIMULATION (1)
ANALYTICAL MODEL (1)
ANTIREFLECTION PATTERNS (1)
ARGON LASER (1)
BACK GATE VOLTAGES (1)
BALLISTIC CONDUCTORS (1)
BASE GENERATION LIFETIME (1)
BASE LENGTH (1)
BIAS TEMPERATURE INSTABILITY (1)
BIAS TEMPERATURE INSTABILITY DEGRADATION (1)
BIPOLAR TRANSISTORS (1)
CARRIER TRANSPORT (1)
CHANNEL LENGTH (1)
CHARGE CARRIER MOBILITY (1)
CHARGE CARRIER PROCESSES (1)
CHEMICAL VAPOUR DEPOSITION (1)
CMOS LIKE CIRCUIT (1)
CMOS SCALING (1)
COMBINED BIPOLAR MOS TRANSISTORS (1)
CONDUCTION BAND (1)
CONDUCTION BANDS (1)
CONTACT POTENTIAL (1)
CRYOGENIC ELECTRONICS (1)
CRYSTAL GROWTH (1)
DEFECT LOCALISATION (1)
DEGRADATION (1)
DEVICE FABRICATION (1)
DIGITAL INTEGRATED CIRCUITS (1)
DIGITAL SIMULATION (1)
DOPING FLUCTUATIONS (1)
DOPING-ENHANCED OXIDATION RATE (1)
DOUBLE-GATE FET (1)
DOUBLE-GATE MOSFET (1)
DRAIN BREAKDOWN VOLTAGE (1)
DRAIN RESISTANCE (1)
ELECTRIC BREAKDOWN (1)
ELECTRIC BREAKDOWN OF SOLIDS (1)
ELECTRIC CURRENT (1)
ELECTRIC POTENTIAL (1)
ELECTRON MOBILITY (1)
ETCHING (1)
EXTREME TEMPERATURE RESPONSE (1)
FETS (1)
FIELD EFFECT INTEGRATED CIRCUITS (1)
FIN FET (1)
FINFET (1)
FLASH MEMORY (1)
FLOATING SUBSTRATE (1)
FLUCTUATIONS (1)
FLUORINE IMPLANT (1)
FOCUSED HALOGEN LAMP (1)
GAA (1)
GAMMA-RAY EFFECTS (1)
GAMMA-RAY IRRADIATION (1)
GATE VOLTAGE (1)
GRAIN BOUNDARIES (1)
GRAIN BOUNDARY-FREE (1)
GREEN'S FUNCTION METHODS (1)
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Search results for: J.P. Colinge

Junctionless Nanowire Transistor (JNT): Properties and design guidelines

Analysis of the Low-Frequency Noise of Junctionless Nanowire Transistors operating in saturation

Variable temperature characterization of low-dimensional effects in tri-gate SOI MOSFETs

LDD depletion effects in thin-BOX FDSOI devices with a ground plane

SOI gated resistor: CMOS without junctions

Variable-barrier tunneling SOI transistor (VBT)

Hot carrier (HC) and bias-temperature-instability (BTI) degradation of MuGFETs on silicon oxide and silicon nitride buried layers

Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations

Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET

Multi-Gate SOI MOSFET Operations in Harsh Environments

A Quantum Definition of Threshold Voltage in MuGFETs

Multi-gate SOI MOSFETs

Dose radiation effects in FinFETs

Influence of device geometry on SOI single-hole transistor characteristics

Hall effect measurements in double-gate SOI MOSFETs

High-temperature instability processes in SOI structures and MOSFETs

Self-aligned silicon-on-insulator nano flash memory device

Recombination Current and Carrier Lifetime Extraction in Dual-Gate Fully Depleted SOI Devices

Silicon-On-Insulator-Based Technology MOSFET : Prospects For Application to Low Noise RF Integrated Circuits

Comparison of self-heating effect in GAA and SOI mosfets

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