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Nitride program charge effects on random telegraph noise (RTN) in SONOS flash cells are investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a wide spread in RTN amplitude after programming while a floating gate flash cell has identical RTN amplitude in erase and program states. The spread of program-state...
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can...
Endurance considerations induced by the degradation of top and bottom oxides are proposed for a SONOS memory. First, a correlation is found between the widespread C-V curves induced by interface generation and cycling numbers (cyc. #). Unlike VFB (accumulation region), VT (inversion region) shows a much severe shift. Interface state (Nit) is identified as a key factor even when a 2 nm bottom oxide...
Erase characteristics of a SONOS-based structure are emulated not only for n+-poly and p+-poly gates but also for TaN-gate+Al2O3 combination. By incorporating our previous studies, performances including program, erase, and read disturb can be reviewed for both SONOS and TANOS devices. Unsurprisingly, it is hard to satisfy all requirements by using a SONOS device. In a TANOS device, an optimal bottom...
Program-charge effects in a SONOS Flash cell on the amplitude of random telegraph noise (RTN) are investigated. We measure RTN in 45 planar SONOS cells and 40 floating-gate (FG) cells in erase state and program state, respectively. We find that a SONOS cell has a wide spread in RTN amplitudes after programming, while an FG cell has identical RTN amplitudes in erase and program states at the same read-current...
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