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A novel low-voltage, hot-carrier programming method for NAND flash cell is presented. By suitably controlling the NAND string's conductance, a sufficient program current along with a high heating field is induced to cause efficient hot-carrier injection. Comprehensive studies on bias and timing effects are performed on 75nm-node floating-gate NAND cells. This programming method greatly alleviated...
Reliability of charge trapping (CT) devices has been examined in detail, and the path to sub-30nm NAND flash is investigated. All CT devices are vulnerable to edge effects (non-uniform injection and non-uniform Vt along the device width). This degrades both the endurance and the ISPP programming efficiency, but the effect can be minimized by careful engineering. Metal gate and high-K dielectric can...
A novel bias scheme is proposed for non-volatile memory cells arranged in a virtual-ground array that utilizes hot-carrier injections for program and erase operations. By taking two adjacent cells on the same wordline as a unit, and letting the commonly shared n+ region being floating during program and erase, punchthrough immunity is greatly improved. Program/erase speed, endurance, and retention...
We have successfully fabricated and characterized sub-30 nm and sub-20 nm BE-SONOS NAND flash. Good device characteristics are achieved through two innovative processes: (1) a low-energy tilt-angle STI pocket implantation to suppress the STI corner edge effect, and (2) a drain offset using an additional oxide liner to improve the short-channel effect. The conventional self-boosting program-inhibit...
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