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A Cluster Timing Algorithm has been developed in order to store information coming from a 6 bits, 1 Gsample/s flash ADC. In particular the algorithm detects signal peaks and stores their amplitude and timing information. A Xilinx ML605 Evaluation Board, making use of a FPGA Virtex 6 core, has been employed in order to develop and test the VHDL code. The final goal is to develop a VME board capable...
The counting of the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Up to now the bottleneck for the application of this technique was the possibility of realizing a large number of very-fast read-out channels with reduce power consumption. Typical time separation between each ionization act in a helium-based gas mixture is from...
In this paper a 6 bits, 1 GSa/s flash ADC is presented. It is included in a front end for drift chambers. The front-end has been designed in a 0.13 μm CMOS technology with 1.2 V supply voltage. The single circuit blocks are described in detail. The ENOB is 5.86 bits, while the overall power consumption is 58.1 mA.
The counting of the consecutive ionization clusters in a drift chamber is a very promising technique for particle identification purposes. Although this technique features a number of advantages, the bottleneck for its implementation is represented by the difficulties in realizing a low cost, high-speed electronic interface. In fact, typical time separation between each ionization act in a helium-based...
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