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This paper presents a 672-bit electrically erasable programmable read-only memory (EEPROM) fabricated using a conventional 0.13 μm CMOS process. The write voltages are lowered to 6 V and -4 V using the proposed planar cell structure on the isolated p-wells. The amount of electrons removed from the floating gate is regulated by real-time monitoring to reduce the Vth variation of erased cells...
This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction,...
A transceiver for a memory controller operating at 16 Gb/s per link is implemented in 65 nm CMOS process. Timing calibration, equalization and diagnostic circuits for both memory read and write are on the controller to optimize the overall system performance and cost. A 5-tap TX FIR and a continuous time RX equalizer with active inductor loads are employed. The transceiver also includes a diagnostic...
An asymmetric memory interface cell with 32 bidirectional data and four unidirectional request links operating at 16 Gb/s per link is implemented in TSMC 65 nm CMOS process technology. Timing adjustment and equalization circuits for both memory read and write are on the controller to reduce the memory cost. Each link operates at a maximum rate of 16 Gb/s with sufficient and comparable margins in both...
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