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In this paper, we present a novel methodology for identifying lithography hot-spots and automatically transforming them into the lithography-friendly design space. This fast model-based technique is applied at the mask tape-out stage by slightly shifting and resizing the designs. It implicitly does a similar functionality as that of the Process Window OPC (PWOPC) but more efficiently. Being a relatively...
Today, many of the approaches that are commonly referred to as physical DFM techniques only address catastrophic defects and systematic process variations. These techniques include spreading wires, doubling vias, identification of critical areas in the circuit that are especially susceptible to defects, and identification of proximity effects caused by the lithography process. However, physical DFM...
In double patterning lithography, overlay error between two patterning steps at the same layer results in critical dimensions variability. In order to optimize the yield loss due to overlay error, statistical design techniques should be applied since overlay error is segueing from a systematic error into a random one for technology nodes smaller than 45-nm. In this paper, the effects of overlay error...
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