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We propose and demonstrate by numerical simulations a dynamic polling algorithm to maximize the TCP throughput of 10G-EPON, which can optimize the polling cycle by considering the bandwidth utilization and the round-trip time.
The test to verify the making performance of high voltage switchgear is required and the standard also requires the making test. We have developed a large current making switch (rated voltage of 180 kV, trigger energy of 5.5 kJ) to mainly apply to making tests of high voltage switchgears, such as short-circuit making and out-of-phase. In this kind of test is important that the gap withstand high voltage...
A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEL' soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET...
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