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This paper proposes a new ladder FeRAM ar chitecture with capacitance-coupled-bitline (CCB) cells for high-end embedded applications. The ladder FeRAM architecture short-circuits both electrodes of each ferroelectric capacitor at every standby cycle. This overcomes the fatal disturbance problem inherent to the CCB cell, and halves read/write cycle time by sharing a plateline and its driver with 32...
Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128 Mb chain FeRAMtrade with SDRAM-compatible 1.6 GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching...
Difficulty to achieve high density FeRAMs with sub-micron ferroelectric capacitors is widely understood due to damage to the capacitors. Key process techniques such as high quality ferroelectric film deposition, electrode preparation, capacitor RIE and hydrogen barrier structure formation are introduced for 64M FeRAMs with sub micron high reliability PZT capacitors.
An excellent 64Mb chain FeRAMtrade using a highly reliable capacitor with damage-robust MOCVD-PZT and SrRuO3/IrO2 top electrode (TE) is successfully demonstrated for the first time. A very large signal margin of 540mV at 1.8V is achieved for the capacitor as small as 0.19mum2. Large sensing margin is well maintained after 85degC storage, and 10 years lifetime is successfully guaranteed. The combination...
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