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Leakage power loss is a major concern as it drains the battery even when a circuit is completely idle. Efficient leakage control mechanisms are necessary to maximize battery life. In this paper, the design and characterization of an ultra-low power combinational CMOS standard cell library is presented. A novel technique that achieves cancellation of leakage effects in both the pull-up network (PUN)...
With the migration to deep sub-micron (DSM) process technologies, the static power (leakage) has become the major contributor to the design's overall power consumption. In this work, we show experiments that illustrate the significant increase in the ratio of the leakage to the total power as the DSM process nodes shrink. We also present a high-level design/synthesis method, called power islands that...
This work introduces a high-level synthesis (HLS) methodology that eliminates the spurious switching activity (SSA) and the leakage in a great portion of the resulting circuit through the use of power islands. A power island is a cluster of logic whose power can be controlled independent from the rest of the circuit, and hence can be completely powered down when all of the logic contained within it...
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