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A large-swing, high-driving, low-power, class-AB buffer amplifier, which consists of a high-gain input stage and a unity-gain class-AB output stage, with low variation of quiescent current is proposed. The high-driving capability, low power consumption and low variation of the quiescent output current are achieved by using adaptive-gain error amplifiers whose gains are small in the vicinity of the...
A phase-locked loop (PLL), in which the ripple in the control voltage is suppressed to minimize the output phase jitter, is proposed. A discriminator-aided edge detector is added in the PLL to switch the outputs of the loop filter to reduce the ripple. The proposed PLL and the conventional circuit have been implemented in a 0.35-mum CMOS process. Compared with the conventional PLL, the rms jitter...
A high-speed low-power rail-to-rail class-B buffer amplifier, which is suitable for liquid crystal display applications, is proposed. The summing circuit is biased by the constant current sources to applicable different supply voltages. The buffer draws little current while static but has a large driving capability while transient. The circuit achieves the large driving capability by employing simple...
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