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Estimation of resistance of power devices has become critical for improving the efficiency of on-chip power-management circuits. In this paper, we present an efficient technique for estimation of resistance of a large lateral power-array layout along with parasitics. We extract a resistive network for metalizations utilizing the finite-element method. The method primarily benefits in terms of computational...
An accurate and fast technique for estimation of resistance from a large lateral power array layout along with parasitics and interconnects is presented in this paper. We extract a resistive network for metallization utilizing the finite element method (FEM). The technique benefits in terms of computation from exploitation of the repetitive nature of metallization in a power array layout. Device channels...
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