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A Monte Carlo simulation shows that a DRAM using the floating body cell (FEC) realizes a 333MHz high-speed random cycle with an introduction of a symmetrical sense amplifier circuit and optimization of its current mirror ratio. Since the FEC DRAM having a superior affinity with logic LSI process is also shown to have its macro size smaller than the conventional 1T-1C DRAM, the FEC is a promising candidate...
In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also, they disturb normal DRAM accesses leading to performance degradation. In order to overcome this problem, we propose several DRAM refresh architectures. The basic idea is to eliminate unnecessary DRAM refreshes...
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