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In this paper, an ultra-low-leakage TFET/CMOS hybrid Dual-Port SRAM (DPSRAM) based scratchpad memory is proposed. DPSRAM cells are designed using TFETs to reduce the leakage power in the memory array as compared to CMOS. Peripheral circuits are designed using 28nm FDSOI technology to increase speed and to reduce area as compared to full TFET based memories. Performance and stability of the memory...
Dynamic variability of 28nm FD-SOI high density SRAMs has been directly measured and carefully modeled using a new technique based on the Supply Read Retention Voltage (SRRV) metric. It is proven that, for this technology, N&PBTI induced variability has only a small impact on the SRAM read stability after 10 years working at operating conditions.
A novel hybrid memory architecture - Non-Volatile SRAMs (NVSRAMs) wherein resistive memories incorporated as an integral part of SRAM cell to provide information back-up feature is presented in this paper. It also makes a discussion on some of the challenges faced in implementing hybrid memories and the prospective solutions.
The paper presents a new methodology to model the dynamic variability of SRAM cell in 28nm FDSOI technology. This approach can be easily integrated into SPICE and used for circuit degradation simulation. It is based on two successful models that showed good correlation with experimental data. Using only stress measurements made at transistors level we are able to simulate the degradation obtained...
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