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In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180 nm technology, the proposed design is able to decode QCIF 30 fps at 1.5 MHz. It...
This paper presents a systematic, power-efficient design methodology for the complex finite state machine (FSM) implementation of H.264/AVC decoding. The proposed FSM orchestrates the decoding steps and predicts the type of incoming codeword based on current FSM states and input symbols. The VLSI realization shows a gate count reduction of 14% and an average power reduction of 37.6% in real-time video...
In this paper, we propose a power-efficient bitstream parsing for H.264/AVC baseline profile decoding. It parses the input bitstream syntaxes and controls the following decoding steps. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, clock gating etc., have been adopted in our...
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