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A 1Gs/s CMOS track-and-hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65 nm low-power CMOS process, exhibits a total...
This paper presents a comparison between BiCMOS and CMOS op-amps to be employed in pipelined analog-to-digital converters. Single and two-stage architectures were considered; in addition, a couple of op-amps exploiting bipolar devices in the input stage are proposed. The amplifiers were designed for the first stage of a 12-b high-speed converter; op-amps are constrained by a fixed power budget and...
This paper describes an accurate model for the systematic design and the simulation of high-resolution pipelined ADCs. The design is based on the non-linearities affecting the ADC whereas the goal is the evaluation of the best architecture matching the specifications (DNL and INL). Bit partitioning along pipeline chain, amplifiers specifications (designed down to transistor-level in both CMOS and...
A 6-bit time-interleaved analog-to-digital converter for ultra-wide band applications is proposed. The structure consists of seven successive approximation A/D converters designed to pursue high speed and low power consumption. A merged-capacitor technique is implemented in the DAC, while the successive approximations register is based on a single-row architecture with D-FF's. The converter, designed...
The brief presents the design and the implementation of a very-high speed track-and-hold amplifier (THA) for analog-digital converters with high input bandwidth. The THA is based on a half-bridge driving a switched-emitter follower. A lower power consumtpion and a simpler circuit architecture than previously reported bipolar implementations were achieved by means of circuit optimization. In particular,...
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