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Linearity testing of high resolution analog-to-digital Converters (ADCs) requires test instrumentation that has high precision digital-to-analog conversion (DAC) capability. Further, a large number of samples need to be collected for linearity testing of high resolution ADCs (18-24 bit) to guarantee test quality. In this paper a novel fast linearity testing approach is proposed for testing high resolution...
Random jitter, present in the clock that is used for sampling the input signal, applied to the A/D converter results in noise that is added to the output of the device. For high-resolution A/D converters (low quantization noise), a very low-jitter clock is needed to measure accurate signal-to-noise ratio. Low jitter constraints on the clock signal increases with the test stimulus frequency. This paper...
This paper proposes a novel methodology for reducing the static linearity test time of SAR A/D converters. Due to the low data conversion rate and high resolution, the test time required measuring the linearity specifications such as INL and DNL in SAR A/D converters can be as high as 40% of the total A/D converter test time. The proposed method is based on the fact that the non-idealities in the...
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