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The stress effect at the channel region of pFETs with compressive stress liner (c-SL) and eSiGe using replacement gate technology is firstly investigated in detail based on the combination of UV-Raman spectroscopy and 3D stress simulation. The gate length effect for the channel stress is confirmed by measurement and simulation. Moreover, the Ion dependence on the channel width is also investigated...
A raised source/drain extension (RSDE) pFET on (110) Si wafer is demonstrated for the first time with in-situ doped selective epitaxy technology. Roll-off has been effectively improved, resulting from the elimination of ion channeling in (110) Si. Due to the hole mobility enhancement and parasitic resistance reduction, ion of 389muA/mum (Vd= -1.0 V) has been achieved at Lmin around 30nm extracted...
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