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We report on aggressively scaled RMG-HKL devices, with tight low-VT distributions [σ(VTsat) ∼ 29mV (PMOS), ∼ 49mV (NMOS) at Lgate∼35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen...
We report on gate-last technology for improved effective work function tuning with ∼200meV higher p-EWF at 7Å EOT, ∼2x higher fmax performance, and further options for channel stress enhancement than with gate-first by taking advantage of the intrinsic stress of metals and gate height dependence. Additional key features: 1) scavenging technique yielding UT-EOT down to ∼5Å is demonstrated in gate-last,...
We discuss several advancements over our previous report (S. Kubicek, 2006): - Introduction of conventional stress boosters resulting in 16% and 11% for nMOS and pMOS respectively. For the first time the compatibility of SMT (stress memorization technique) with high-kappa/metal gate is demonstrated. In addition, we developed a blanket SMT process that does not require a photo to protect the pMOS by...
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