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This work surveys our 2005-2009 experimental contributions to develop a combined altitude and underground test platform devoted to the soft-error rate (SER) characterization of deca-nanometer CMOS technologies. The platform currently involves two complementary sites to separate the component of the SER induced by the cosmic rays from that caused by on-chip radioactive impurities: the Altitude SEE...
We report real-time SER characterization of CMOS 65 nm SRAM memories in both altitude and underground environments. Neutron and alpha-particle SERs are compared with data obtained from accelerated tests and values previously measured for CMOS 130 nm technology.
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