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Multi-core processor Simulation Platform is always a very important tool in modern multi-core processor design for the system-level design and evaluation. In this paper, a multi-core processor simulator is proposed by modifying Simple Scalar v3.0to simulate parallelized multi-core programs. Shared memory is used for the communication between different cores, which is the communication network among...
In this paper, a simple, efficient, low power off-chip memory design is proposed, which fully exploits the features of DRAM memory and video application, as well as overcomes the drawbacks of algorithm complexity and system modification of embedded compression, which is a popular way to decrease power consumption of the off-chip memory. The integration of the scheme into video decoder will not involve...
H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization, and can be used to fit well with the requirements for this decoder. To simulate and evaluate...
In this paper, a functional model of SystemC-based MPEG-2 decoder is presented, which is of heterogeneous multi-IP-cores and hybrid-interconnections. Considering the application-specific features into the design flow, three important aspects are analyzed, including function partition, parameter sharing, and interconnection topology, which are the key technical difficulties in the system level design...
A novel lossless frame recompression method and an efficient memory address mapping scheme for frame storage are proposed, which can reduce the Read/Write and row activation operations of the external memory. The proposed scheme has been verified with MPEG-2 based HDTV video decoder. Without video quality degradation and the increasing of reading bytes from off-chip memory, the number of bytes writing...
A major bottleneck of MP@HL MPEG-2 decoder is the memory bandwidth. It is important to improve the utilization ratio of the memory bandwidth in MPEG2 decoder. To realize it, a new memory storing architecture is proposed in this paper. Since the number of overhead cycles needed for row-activations in SDRAM can be minimized, the memory bandwidth can be improved significantly. Compared with the linear...
In an H.264 video encoder, motion estimation (ME) is the most time-consuming component. Several fast ME algorithms have been proposed to reduce the complexity of integer pixel ME (IME) computation, but few of them considered IME and fractional pixel ME (FME) together. Given the possibility of performance improvement through designing both IME and FME at the same time, a new hardware architecture is...
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