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Multi-core processor Simulation Platform is always a very important tool in modern multi-core processor design for the system-level design and evaluation. In this paper, a multi-core processor simulator is proposed by modifying Simple Scalar v3.0to simulate parallelized multi-core programs. Shared memory is used for the communication between different cores, which is the communication network among...
Shrinking the feature size allows more and better functions on a single chip. However, it makes multiprocessor system-on-chip (MPSoC) more susceptible to various reliability threats. Power supply noise is a major reliability problem faced by low power MPSoCs using power gating techniques. Powering on and off a processing unit in MPSoCs will induce large power/ground (P/G) noise and can cause timing...
3D multi-processor system-on-chip (3D MPSoC) can integrate more PUs together with shorter interconnection using vertical interconnection. It's very important to analyze the power ground (P/G) noise induced by power gating in low power 2D MPSoC. Actually, 3D MPSoC will be more sensitive to P/G noise due to the vertical interconnection between different PUs. So the P/G noise induced by power gating...
As technology scaling, more processing units (PUs) are integrated in multiprocessor system-on-chip (MPSoC) to achieve higher performance. Due to the higher variations resulted from reducing feature sizes and the needs of lower power consumption, on-chip monitoring of environmental information, such as thermal, voltage, and frequency, is becoming increasingly important. To address this need, sensors...
To cope with the soft errors and make full use of the multi-core system, this paper gives an efficient fault-tolerant hardware and software co-designed architecture for multi-core systems. And with a not large number of test patterns, it will use less than 33% hardware resources compared with the traditional hardware redundancy (TMR) and it will take less than 50% time compared with the traditional...
Vehicle-based pedestrian detection system receives more and more attentions in road safety applications of the modern intelligent transportation system. However, the existed detection algorithms are too computing extensive for single core vehicle-based processors. As the promising multi-core architecture provides both energy efficient and powerful computing solutions, it is relevant to evaluate the...
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