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This work demonstrates the successful integration of 0.85nm-EOT Si0.45Ge0.55-pFETs using a gate first approach. An in-depth analysis, ranging from capacitor-level up to circuit-level is carried out, with systematic benchmarking to a conventional Si-channel reference. Outperforming the state-of-the-art Si0.55Ge0.45-pFETs, an ION of 630μA/μm at LG_POLY = 35nm with IOFF = 100nA/μm and VDD = -1V has been...
A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO2 based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and Tinv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at Ioff=100 nA/μm with VDD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further...
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