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In this paper, we present a new low-latency asynchronous pipeline control circuit. The control circuit has only two gate delays in its critical path, which is faster compared to other works reported in the literature. Two applications of the design are shown to demonstrate its efficiency. The first is a 16-bit FIFOs and the second is a 4times4 multipliers which are designed both using LLA and GasP...
This paper presents a resource allocation technique to design low-power register-transfer-level datapaths. The basis of this technique is to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles, to partition the circuit into n disjoint modules and assign each module to a distinct clock, and to operate each module only during its corresponding...
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