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Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFET and NFET over the lifetime of usage, leading to performance and reliability degradation of nanoscale CMOS SRAM. In addition, most of the state-of-the-art SRAM designs employ replica timing control circuit to mitigate the effects of leakage and process variation, optimize the performance, and reduce...
The contact resistance of CMOS device increases sharply withtechnology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-kappa metal-gate devices over the lifetime of usage...
The threshold voltage (VT) drift induced by negative bias temperature instability (NBTI) weakens PFETs, while positive bias temperature instability (PBTI) weakens NFETs fabricated with high-k metal-gate, respectively. These long-term VT drifts degrade SRAM cell stability, margin and performance, and may lead to functional failure over the life of usage. Additionally, most state-of-the-art SRAMs are...
We have analyzed impacts of NBTI on power-gated SRAM arrays in terms of RSNM, WM, power, performance, and wake-up time. We also studied PMOS-type pre-charge circuit degradation, and compared two basic sensing amplifier structures when they were under NBTI stress. Our results indicated that VT drift of power switch degraded RSNM but improved WM in power-gated SRAM. Signal probability of unselected...
The threshold voltage (VT) drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM over the lifetime of usage. Moreover, most state-of-the-art SRAMs employ replica timing control scheme to mitigate the effects of excessive leakage and variation, and NBTI/PBTI induced VT drifts can render...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
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