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A new circuit structure for the realisation of an analogue four-quadrant voltage divider with improved dynamic performance is proposed. The structure was developed on the basis of the augmented Lagrangian method and the gradient optimisation approach. The circuit is especially suited for monolithic IC implementation by employing the CMOS switched-capacitor (SC) techniques. The device has been built...
A new method for significantly reducing the effect of nonlinear errors on the performance of an analogue multiplier is presented. The method is especially well suited for switched-capacitor devices where time-shared (multiplexing) techniques can be easily employed. However, the method is quite general in nature and can be applied to any type of analogue integrated multiplier. The effectiveness of...
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