The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Over the past few decades, CMOS technology has mainly been driven by transistor scaling. However, the scaling benefits of conventional bulk MOSFETs come at the cost of increased short channel effects, degrading their performance as a switch. In order to counter such effects, device structures with enhanced gate control of the channel have been proposed. A double-gate (DG) MOSFET is one such structure...
As transition is being made into 22 nm node, technology considerations and device architectures suitable for such scaled technologies are being explored. To design circuits and systems at scaled nodes, we believe there is a need for technology aware circuit and system design methodology that considers device architecture, and technology challenges to achieve design optimality. In this paper, we discuss...
Spin-Torque Transfer Magnetic RAM (STT MRAM) has emerged as a promising candidate for future universal memory. It not only combines the desirable attributes of all current memory technologies (SRAM, DRAM and flash memories) but also solves the critical drawbacks of conventional MRAM technology: poor scalability and high write current. However, variations in process parameters can lead to large number...
Non-uniform temperature profile generated by hot- spots affect the nearby units in a chip. Different sections of a large sized cache memory would experience different failure statistics due to their proximity to the hot-spots. The nano-scaled SRAM (Static Random Access Memory) cell stability is analyzed systematically under such 'spatial' temperature variations for different technologies. The bitcell...
In an SRAM array, the systematic inter-die and the random within-die variations in process parameters cause significant number of parametric failures, to degrade process yield in the nanometer technology regime. In this paper, we investigate the interaction between the inter-die and intra-die Vt variations on SRAM read and write failures. To improve robustness of SRAM cell, we propose a closed-loop...
We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance. In order to improve the data retention capability of un-selected cells during write, the power supply lines of memory cells in one column are connected to each...
We propose a novel Schmitt Trigger (ST) based fully differential 10 transistor SRAM (Static Random Access Memory) bitcell suitable for sub-threshold operation. The proposed Schmitt trigger based bitcell achieves 1.56X higher read static noise margin (SNM) (VDD = 400mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built in process variation tolerance that...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.