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Over the past few decades, CMOS technology has mainly been driven by transistor scaling. However, the scaling benefits of conventional bulk MOSFETs come at the cost of increased short channel effects, degrading their performance as a switch. In order to counter such effects, device structures with enhanced gate control of the channel have been proposed. A double-gate (DG) MOSFET is one such structure...
As transition is being made into 22 nm node, technology considerations and device architectures suitable for such scaled technologies are being explored. To design circuits and systems at scaled nodes, we believe there is a need for technology aware circuit and system design methodology that considers device architecture, and technology challenges to achieve design optimality. In this paper, we discuss...
In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, degrading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the...
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