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Over the past few decades, CMOS technology has mainly been driven by transistor scaling. However, the scaling benefits of conventional bulk MOSFETs come at the cost of increased short channel effects, degrading their performance as a switch. In order to counter such effects, device structures with enhanced gate control of the channel have been proposed. A double-gate (DG) MOSFET is one such structure...
Non-uniform temperature profile generated by hot- spots affect the nearby units in a chip. Different sections of a large sized cache memory would experience different failure statistics due to their proximity to the hot-spots. The nano-scaled SRAM (Static Random Access Memory) cell stability is analyzed systematically under such 'spatial' temperature variations for different technologies. The bitcell...
We propose a novel Schmitt trigger (ST) based differential 10-transistor SRAM (static random access memory) bitcell suitable for subthreshold operation. The proposed Schmitt trigger based bitcell achieves 1.56 x higher read static noise margin (SNM) ( Vdd = 400 mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process variation tolerance that...
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