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Technology scaling beyond the 65nm regime has resulted in leakage power consumption emerging as a major design constraint. Several methods aiming at mitigating leakage power have been studied and tested. These include power-rail gating, input vector control, transistor body biasing, transistor stacking, etc. This paper extends the idea of transistor stacking but limiting it to the inverters in the...
Leakage power dissipation and stability continues to be a major concern in deep-submicron SRAM cell design. In this paper, a quasi-power-gating approach that reduces the leakage power dissipation in an SRAM cell while maintaining stability is proposed. As compared to a standard 6-transistor SRAM, it consists of four additional NMOS transistors. In the active mode, the cell is activated by enabling...
In deep sub-100nm technologies, the exponential increase of static leakage current pose serious design challenges as we try to build efficient low power systems with faster memory cores. Consequently, it is imperative to design systems that adopt leakage control techniques during both standby and active mode. In the recent past, the size of memory cores also has been increasing at a very rapid pace...
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