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The current industry trends towards reducing feature size and increasing integration density call for the use of copper (Cu) metallization and low permittivity (low-k) interlayer dielectrics (ILD). Low-k dielectrics are typically characterized by low mechanical strength, low hardness and high porosity (Blaine et al., 2002). The thermal mismatch stresses induced by the manufacturing process pose significant...
This paper describes methodology for constructing compact SPICE models as a function of process parameter variations. The methodology involves global extraction of process-dependant SPICE model parameters from silicon calibrated TCAD simulations. The model is validated by comparing device characteristics from the extracted SPICE parameters with those from TCAD simulations. The analysis demonstrates...
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