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We present a prototype chip built in a 40 nm CMOS process for readout of a pixel detector. The prototype chip has a matrix of 18×24 pixels with a pixel pitch of 100 µm. It can operate in both: the single photon counting (SPC) mode and the C8P1 mode. In the SPC mode using the high gain setting the measured ENC is 84 e− rms (for the peaking time of 48 ns), the gain is 79.7 µV/e−, while the effective...
Hybrid pixel detectors are becoming a standard in modern fast X-ray imaging for material science, physics and medicine. However, charge sharing effect is the main limitation in increasing position resolution of these systems and also for using them for spectroscopy applications. In this paper we present novel algorithms which allow proper hit allocation even in the case of charge sharing and which...
Existence of the natural diffusive spread of charge carriers on the course of their drift towards collecting electrodes in planar, segmented detectors results in a division of the original cloud of carriers between neighboring channels. This paper presents the analysis of algorithms, implementable with reasonable circuit resources, whose task is to prevent degradation of the detective quantum efficiency...
Presents a collection of slides covering the following topics: 3D IC multiproject fabrication; high energy physics; circuit bonding; wafer thinning; TSV; radiation detector; CMOS; wafer bonding; and SOI process.
This paper reports on the current status of the development of International Linear Collider vertex detector pixel readout chips based on multi-tier vertically integrated electronics. Initial testing results of the VIP2a prototype are presented. The chip is the second embodiment of the prototype data-pushed readout concept developed at Fermilab. The device was fabricated in the MIT-LL 0.15 μm fully...
This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 ×2.5mm2 large...
The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and...
We report on the design and characterization of a new ASIC for the RatCAP, a head-mounted miniature PET scanner intended for neurological and behavioral studies of an awake rat. The ASIC is composed of 32 channels, each consisting of a charge sensitive preamplifier, a 5-bit programmable gain in the pole-zero network, a 3rd order bipolar semi-Gaussian shaper (peaking time of 80 ns), a timing and energy...
A portable system for monolithic active pixel sensors characterization has been developed, its main feature is flexibility. This system can be used for all prototypes test stages, from functional test on wafer to tracking performance measurement with our beam telescope. It is built around a VME data acquisition system and ADC boards 12-bit 20 MHz. System control GUI, on-line monitoring, and data storage...
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