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This paper presents a 64-state, 1/2-rate asynchronous Viterbi decoder suitable for wireless and mobile applications. The decoder uses a novel dynamic Current Sensing Completion Detection (CSCD) technique and achieves significant power reduction while maintaining speed. The decoder, implemented in a 90 nm CMOS technology, occupies an area of 0.81 mm2 and operates at 378 Mb/s while consuming 45 mW:...
This paper describes the implementation of an asynchronous 64-state, 1/2-rate Viterbi decoder using an original architecture and design methodology. The decoder is intended for wireless communications applications, where bit rates over 100 Mb/s and minimum power consumption are sought. The choice of an asynchronous design was predicated by the power and speed advantages of such a methodology. Asynchronous...
SiGe heterojunction bipolar transistors (HBTs) with very thin n+ hydrogenated amorphous Si (α-Si:H) emitters and various doping and Ge distribution profiles in the bases are reported. An analytical model defining the leverage of the structures in terms of current gain and high Early voltage is presented and verified experimentally. Devices having a base doping concentration of 1??1019cm-3, a base...
The first SiGe p-MOSFETs with triangular Ge profiles, fabricated in a Si CMOS-compatible LOCOS isolated process are reported. The feasibility of triangular profiles with peak Ge mole fractions as high as 50% is demonstrated for both CVD and MBE MOSFETs. The transconductance of 3 ??m devices with 0-40% Ge profiles is 34 mS/mm, 100% higher than that of the corresponding Si p-MOSFET fabricated on the...
Techniques for significantly enhancing the speed of CMOS differential pass-transistor logic (DPTL) are presented. Use is made of the noise immunity features of DPTL to enable signal swing reductions that result in increased speed. A novel single-phase clocking scheme using a new DPTL buffer is proposed. Experimental results are provided for a DPTL divide-by-N prescaler (1 ?? N ?? 64) implemented in...
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