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The huge amount of test data of a modern chip produced during manufacturing test could be mined for valuable information about the device under test (DUT), far more than the pass/fail information of each test item. Exploring the hidden correlations and patterns in the test data allows better understanding of the DUT and could therefore lead to test cost reduction or test quality improvement. There...
Virtual Probe (VP), proposed for characterization of spatial variations and for test time reduction, can effectively reconstruct the spatial pattern of a test item for an entire wafer using measurement values from only a small fraction of dies on the wafer. However, VP calculates the spatial signature of each test item separately, one item at a time, resulting in very long runtime for complex chips...
We propose a comprehensive yet low-cost solution for online detection and diagnosis of permanent faults in on-chip networks. Using error syndrome collection and packet/flit-counting techniques, high-resolution defect diagnosis is feasible in both datapath and control logic of the on-chip network without injecting any test traffic or incurring significant performance overhead.
There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently...
Face annotation of photos, a key enabling technology for many exciting new applications, has been gaining broad interest. The task is different from the general face recognition problem because the dataset is not constrained - an unlabelled face may not have any corresponding match in the training set. Moreover, faces in real-life photos have a significantly wider variation range than those in the...
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