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The race to deep sub-micron CMOS technology has resulted in a change in device architectures, from a planar structure to a FinFET to achieve decreased leakage, further downscaling, and better sub-threshold slope, even under a lower power supply [1]. Downscaling trends have forced the analog semiconductor industry to move to the digital domain to maintain functionality in light of increasing short-channel...
A single loop low tracking jitter pixel clock generator is demonstrated in 28nm CMOS process. The proposed architecture only consists of a conventional single loop wide bandwidth fractional-N PLL and two synchronization skills which suppress the tracking jitter and bring out the delay control function like a DLL. When a 250MHz pixel clock is generated and synchronized with a 10kHz HSYNC, the measured...
As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been several approaches to convert analog systems to their digital counterparts and a high-resolution time-to-digital converter (TDC) is a key element for the digitalization of analog...
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