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The adder circuit is used as a main component in the multiplier circuits. The Baugh-Wooley, Braun and CSA multipliers are designed by using our proposed adder cell. The proposed adder circuit is designed by using Shannon theorem. The multiplier circuits are schematised by using DSCH2 VLSI CAD tool and their layouts are generated by using Microwind 3 VLSI CAD tool. The proposed adder based multiplier...
Static random access memories (SRAMs) comprise an increasingly large portion of modern very large scale integrated (VLSI) circuits. The increasing importance of embedded SRAM is due to its low circuit activity factor, leading to low active power density, and productivity of design. The power consumption has become an important issue and has lead to the development of numerous schemes aimed at limiting...
The increasing market of mobile devices and battery powered portable electronic systems is creating demands for chips that consume the smallest possible amount of power. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The power consumption and speed of SRAMs are important issue that has lead to multiple designs with the purpose of minimizing...
This paper presents an error tolerant hardware efficient VLSI architecture for bit parallel systolic multiplication over dual base, which can be pipelined. This error tolerant architecture is well suited to VLSI implementation because of its regularity, modular structure, and unidirectional data flow. The length of the largest delay path and area of this architecture are less compared to the bit parallel...
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These constraints determine both the minimum cell size and supply voltage. RCM is set by the maximum read access time over the array. The randomness of transistor threshold voltages, and thus read times, makes maximum read time...
In this paper we have analyzed an 8-bit multiplier circuit using non clocked pass gate families with help of carry save multiplier (CSA) technique. The multiplier cell of the adder is designed by using pass transistors (n-transistors), p-transistors used as cross-coupled devices. The adder cell is designed by using multiplexing control input techniques. A combination of n- and p-transistors used on...
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